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bc_i2c.c
1 #include <bc_i2c.h>
2 #include <bc_tick.h>
3 #include <stm32l0xx.h>
4 #include <bc_scheduler.h>
5 #include <bc_ds28e17.h>
6 #include <bc_module_sensor.h>
7 #include <bc_system.h>
8 
9 #define _BC_I2C_TX_TIMEOUT_ADJUST_FACTOR 1.5
10 #define _BC_I2C_RX_TIMEOUT_ADJUST_FACTOR 1.5
11 
12 #define _BC_I2C_MEMORY_ADDRESS_SIZE_8BIT 1
13 #define _BC_I2C_MEMORY_ADDRESS_SIZE_16BIT 2
14 #define _BC_I2C_RELOAD_MODE I2C_CR2_RELOAD
15 #define _BC_I2C_AUTOEND_MODE I2C_CR2_AUTOEND
16 #define _BC_I2C_SOFTEND_MODE (0x00000000U)
17 #define _BC_I2C_NO_STARTSTOP (0x00000000U)
18 #define _BC_I2C_GENERATE_START_WRITE I2C_CR2_START
19 #define _BC_I2C_BYTE_TRANSFER_TIME_US_100 80
20 #define _BC_I2C_BYTE_TRANSFER_TIME_US_400 20
21 
22 #define __BC_I2C_RESET_PERIPHERAL(__I2C__) {__I2C__->CR1 &= ~I2C_CR1_PE; __I2C__->CR1 |= I2C_CR1_PE; }
23 
24 static struct
25 {
26  int initialized_semaphore;
27  bc_i2c_speed_t speed;
28  I2C_TypeDef *i2c;
29 
30 } _bc_i2c[] = {
31  [BC_I2C_I2C0] = { .initialized_semaphore = 0, .i2c = I2C2 },
32  [BC_I2C_I2C1] = { .initialized_semaphore = 0, .i2c = I2C1 },
33  [BC_I2C_I2C_1W]= { .initialized_semaphore = 0, .i2c = NULL }
34 };
35 
36 static bc_tick_t tick_timeout;
37 static bc_ds28e17_t ds28e17;
38 
39 static bool _bc_i2c_mem_write(I2C_TypeDef *i2c, uint8_t device_address, uint16_t memory_address, uint16_t memory_address_length, uint8_t *buffer, uint16_t length);
40 static bool _bc_i2c_mem_read(I2C_TypeDef *i2c, uint8_t device_address, uint16_t memory_address, uint16_t memory_address_length, uint8_t *buffer, uint16_t length);
41 static bool _bc_i2c_req_mem_write(I2C_TypeDef *i2c, uint8_t device_address, uint16_t memory_address, uint16_t memory_address_length);
42 static bool _bc_i2c_req_mem_read(I2C_TypeDef *i2c, uint8_t device_address, uint16_t memory_address, uint16_t memory_address_length);
43 static void _bc_i2c_config(I2C_TypeDef *i2c, uint8_t device_address, uint8_t length, uint32_t mode, uint32_t Request);
44 static bool _bc_i2c_watch_flag(I2C_TypeDef *i2c, uint32_t flag, FlagStatus status);
45 static bool _bc_i2c_is_ack_failure(I2C_TypeDef *i2c);
46 static bool _bc_i2c_read(I2C_TypeDef *i2c, const void *buffer, size_t length);
47 static bool _bc_i2c_write(I2C_TypeDef *i2c, const void *buffer, size_t length);
48 static uint32_t bc_i2c_get_timeout_ms(bc_i2c_channel_t channel, size_t length);
49 static uint32_t bc_i2c_get_timeout_us(bc_i2c_channel_t channel, size_t length);
50 static void _bc_i2c_timeout_begin(uint32_t timeout_ms);
51 static bool _bc_i2c_timeout_is_expired(void);
52 static void _bc_i2c_restore_bus(I2C_TypeDef *i2c);
53 
55 {
56  if (++_bc_i2c[channel].initialized_semaphore != 1)
57  {
58  return;
59  }
60 
61  if (channel == BC_I2C_I2C0)
62  {
63  // Initialize I2C2 pins
64  RCC->IOPENR |= RCC_IOPENR_GPIOBEN;
65 
66  // Errata workaround
67  RCC->IOPENR;
68 
69  GPIOB->MODER &= ~(GPIO_MODER_MODE10_0 | GPIO_MODER_MODE11_0);
70  GPIOB->OTYPER |= GPIO_OTYPER_OT_10 | GPIO_OTYPER_OT_11;
71  GPIOB->OSPEEDR |= GPIO_OSPEEDER_OSPEED10 | GPIO_OSPEEDER_OSPEED11;
72  GPIOB->PUPDR |= GPIO_PUPDR_PUPD10_0 | GPIO_PUPDR_PUPD11_0;
73  GPIOB->AFR[1] |= 6 << GPIO_AFRH_AFRH3_Pos | 6 << GPIO_AFRH_AFRH2_Pos;
74 
75  // Enable I2C2 peripheral clock
76  RCC->APB1ENR |= RCC_APB1ENR_I2C2EN;
77 
78  // Errata workaround
79  RCC->APB1ENR;
80 
81  // Enable I2C2 peripheral
82  I2C2->CR1 |= I2C_CR1_PE;
83 
84  bc_i2c_set_speed(channel, speed);
85  }
86  else if (channel == BC_I2C_I2C1)
87  {
88  // Initialize I2C1 pins
89  RCC->IOPENR |= RCC_IOPENR_GPIOBEN;
90 
91  // Errata workaround
92  RCC->IOPENR;
93 
94  GPIOB->MODER &= ~(GPIO_MODER_MODE8_0 | GPIO_MODER_MODE9_0);
95  GPIOB->OTYPER |= GPIO_OTYPER_OT_8 | GPIO_OTYPER_OT_9;
96  GPIOB->OSPEEDR |= GPIO_OSPEEDER_OSPEED8 | GPIO_OSPEEDER_OSPEED9;
97  GPIOB->PUPDR |= GPIO_PUPDR_PUPD8_0 | GPIO_PUPDR_PUPD9_0;
98  GPIOB->AFR[1] |= 4 << GPIO_AFRH_AFRH1_Pos | 4 << GPIO_AFRH_AFRH0_Pos;
99 
100  // Enable I2C1 peripheral clock
101  RCC->APB1ENR |= RCC_APB1ENR_I2C1EN;
102 
103  // Errata workaround
104  RCC->APB1ENR;
105 
106  // Enable I2C1 peripheral
107  I2C1->CR1 |= I2C_CR1_PE;
108 
109  bc_i2c_set_speed(channel, speed);
110  }
111  else if (channel == BC_I2C_I2C_1W)
112  {
114 
116  {
118  }
119  else
120  {
122  }
123 
125 
126  bc_tick_t t_timeout = bc_tick_get() + 500;
127 
128  while (bc_tick_get() < t_timeout)
129  {
130  continue;
131  }
132 
133  bc_ds28e17_init(&ds28e17, BC_GPIO_P5, 0x00);
134 
135  bc_i2c_set_speed(channel, speed);
136  }
137 }
138 
140 {
141  if (--_bc_i2c[channel].initialized_semaphore != 0)
142  {
143  return;
144  }
145 
146  if (channel == BC_I2C_I2C0)
147  {
148  // Disable I2C2 peripheral
149  I2C2->CR1 |= I2C_CR1_PE;
150 
151  // Disable I2C2 peripheral clock
152  RCC->APB1ENR &= ~RCC_APB1ENR_I2C2EN;
153 
154  // Errata workaround
155  RCC->APB1ENR;
156 
157  GPIOB->AFR[1] &= ~(GPIO_AFRH_AFRH3_Msk | GPIO_AFRH_AFRH2_Msk);
158  GPIOB->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEED10_Msk | GPIO_OSPEEDER_OSPEED11_Msk);
159  GPIOB->OTYPER &= ~(GPIO_OTYPER_OT_10 | GPIO_OTYPER_OT_11);
160  GPIOB->MODER |= GPIO_MODER_MODE10_Msk | GPIO_MODER_MODE11_Msk;
161 
162  }
163  else if (channel == BC_I2C_I2C1)
164  {
165  // Disable I2C1 peripheral
166  I2C1->CR1 &= ~I2C_CR1_PE;
167 
168  // Disable I2C1 peripheral clock
169  RCC->APB1ENR &= ~RCC_APB1ENR_I2C1EN;
170 
171  // Errata workaround
172  RCC->APB1ENR;
173 
174  GPIOB->AFR[1] &= ~(GPIO_AFRH_AFRH1_Msk | GPIO_AFRH_AFRH0_Msk);
175  GPIOB->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEED8_Msk | GPIO_OSPEEDER_OSPEED9_Msk);
176  GPIOB->OTYPER &= ~(GPIO_OTYPER_OT_8 | GPIO_OTYPER_OT_9);
177  GPIOB->MODER |= GPIO_MODER_MODE8_Msk | GPIO_MODER_MODE9_Msk;
178  }
179  else if (channel == BC_I2C_I2C_1W)
180  {
181  bc_ds28e17_deinit(&ds28e17);
182 
185  // TODO: deinit bc_module_sensor and bc_ds28e17
186  }
187 }
188 
190 {
191  return _bc_i2c[channel].speed;
192 }
193 
195 {
196  uint32_t timingr;
197 
198  if (_bc_i2c[channel].initialized_semaphore == 0)
199  {
200  return;
201  }
202 
203  if (channel == BC_I2C_I2C_1W)
204  {
205  bc_ds28e17_set_speed(&ds28e17, speed);
206 
207  _bc_i2c[channel].speed = speed;
208 
209  return;
210  }
211 
212  if (speed == BC_I2C_SPEED_400_KHZ)
213  {
214  timingr = 0x301d1d;
215  }
216  else
217  {
218  timingr = 0x709595;
219  }
220 
221  if (channel == BC_I2C_I2C0)
222  {
223  I2C2->CR1 &= ~I2C_CR1_PE;
224  I2C2->TIMINGR = timingr;
225  I2C2->CR1 |= I2C_CR1_PE;
226  }
227  else if (channel == BC_I2C_I2C1)
228  {
229  I2C1->CR1 &= ~I2C_CR1_PE;
230  I2C1->TIMINGR = timingr;
231  I2C1->CR1 |= I2C_CR1_PE;
232  }
233 
234  _bc_i2c[channel].speed = speed;
235 }
236 
237 bool bc_i2c_write(bc_i2c_channel_t channel, const bc_i2c_transfer_t *transfer)
238 {
239  if (_bc_i2c[channel].initialized_semaphore == 0)
240  {
241  return false;
242  }
243 
244  if (channel == BC_I2C_I2C_1W)
245  {
246  return bc_ds28e17_write(&ds28e17, transfer);
247  }
248 
249  I2C_TypeDef *i2c = _bc_i2c[channel].i2c;
250 
251  bc_system_pll_enable();
252 
253  // Get maximum allowed timeout in ms
254  uint32_t timeout_ms = _BC_I2C_TX_TIMEOUT_ADJUST_FACTOR * bc_i2c_get_timeout_ms(channel, transfer->length);
255 
256  _bc_i2c_timeout_begin(timeout_ms);
257 
258  bool status = false;
259 
260  // Wait until bus is not busy
261  if (_bc_i2c_watch_flag(i2c, I2C_ISR_BUSY, SET))
262  {
263  // Configure I2C peripheral and try to get ACK on device address write
264  _bc_i2c_config(i2c, transfer->device_address << 1, transfer->length, I2C_CR2_AUTOEND, _BC_I2C_GENERATE_START_WRITE);
265 
266  // Try to transmit buffer and update status
267  status = _bc_i2c_write(i2c, transfer->buffer, transfer->length);
268  }
269 
270  // If error occured ( timeout | NACK | ... ) ...
271  if (status == false)
272  {
273  // Reset I2C peripheral to generate STOP conditions immediately
274  __BC_I2C_RESET_PERIPHERAL(i2c);
275  }
276 
277  bc_system_pll_disable();
278 
279  return status;
280 
281 }
282 
283 bool bc_i2c_read(bc_i2c_channel_t channel, const bc_i2c_transfer_t *transfer)
284 {
285  if (_bc_i2c[channel].initialized_semaphore == 0)
286  {
287  return false;
288  }
289 
290  if (channel == BC_I2C_I2C_1W)
291  {
292  return bc_ds28e17_read(&ds28e17, transfer);
293  }
294 
295  I2C_TypeDef *i2c = _bc_i2c[channel].i2c;
296 
297  bc_system_pll_enable();
298 
299  // Get maximum allowed timeout in ms
300  uint32_t timeout_ms = _BC_I2C_RX_TIMEOUT_ADJUST_FACTOR * bc_i2c_get_timeout_ms(channel, transfer->length);
301 
302  _bc_i2c_timeout_begin(timeout_ms);
303 
304  bool status = false;
305 
306  // Wait until bus is not busy
307  if (_bc_i2c_watch_flag(i2c, I2C_ISR_BUSY, SET))
308  {
309  // Configure I2C peripheral and try to get ACK on device address read
310  _bc_i2c_config(i2c, transfer->device_address << 1, transfer->length, I2C_CR2_AUTOEND, I2C_CR2_START | I2C_CR2_RD_WRN);
311 
312  // Try to receive data to buffer and update status
313  status = _bc_i2c_read(i2c, transfer->buffer, transfer->length);
314  }
315 
316  // If error occured ( timeout | NACK | ... ) ...
317  if (status == false)
318  {
319  _bc_i2c_restore_bus(i2c);
320  }
321 
322  bc_system_pll_disable();
323 
324  return status;
325 }
326 
328 {
329  if (_bc_i2c[channel].initialized_semaphore == 0)
330  {
331  return false;
332  }
333 
334  if (channel == BC_I2C_I2C_1W)
335  {
336  return bc_ds28e17_memory_write(&ds28e17, transfer);
337  }
338 
339  I2C_TypeDef *i2c = _bc_i2c[channel].i2c;
340 
341  // Enable PLL and disable sleep
342  bc_system_pll_enable();
343 
344  uint16_t transfer_memory_address_length =
345  (transfer->memory_address & BC_I2C_MEMORY_ADDRESS_16_BIT) != 0 ? _BC_I2C_MEMORY_ADDRESS_SIZE_16BIT : _BC_I2C_MEMORY_ADDRESS_SIZE_8BIT;
346 
347  // If memory write failed ...
348  if (!_bc_i2c_mem_write(i2c, transfer->device_address << 1, transfer->memory_address, transfer_memory_address_length, transfer->buffer, transfer->length))
349  {
350  // Reset I2C peripheral to generate STOP conditions immediately
351  __BC_I2C_RESET_PERIPHERAL(i2c);
352 
353  // Disable PLL and enable sleep
354  bc_system_pll_disable();
355 
356  return false;
357  }
358 
359  // Disable PLL and enable sleep
360  bc_system_pll_disable();
361 
362  return true;
363 }
364 
366 {
367  if (_bc_i2c[channel].initialized_semaphore == 0)
368  {
369  return false;
370  }
371 
372  if (channel == BC_I2C_I2C_1W)
373  {
374  return bc_ds28e17_memory_read(&ds28e17, transfer);
375  }
376 
377  I2C_TypeDef *i2c = _bc_i2c[channel].i2c;
378 
379  // Enable PLL and disable sleep
380  bc_system_pll_enable();
381 
382  uint16_t transfer_memory_address_length =
383  (transfer->memory_address & BC_I2C_MEMORY_ADDRESS_16_BIT) != 0 ? _BC_I2C_MEMORY_ADDRESS_SIZE_16BIT : _BC_I2C_MEMORY_ADDRESS_SIZE_8BIT;
384 
385  // If error occurs during memory read ...
386  if (!_bc_i2c_mem_read(i2c, transfer->device_address << 1, transfer->memory_address, transfer_memory_address_length, transfer->buffer, transfer->length))
387  {
388  _bc_i2c_restore_bus(i2c);
389 
390  // Disable PLL and enable sleep
391  bc_system_pll_disable();
392 
393  return false;
394  }
395 
396  // Disable PLL and enable sleep
397  bc_system_pll_disable();
398 
399  return true;
400 }
401 
402 bool bc_i2c_memory_write_8b(bc_i2c_channel_t channel, uint8_t device_address, uint32_t memory_address, uint8_t data)
403 {
404  bc_i2c_memory_transfer_t transfer;
405 
406  transfer.device_address = device_address;
407  transfer.memory_address = memory_address;
408  transfer.buffer = &data;
409  transfer.length = 1;
410 
411  return bc_i2c_memory_write(channel, &transfer);
412 }
413 
414 bool bc_i2c_memory_write_16b(bc_i2c_channel_t channel, uint8_t device_address, uint32_t memory_address, uint16_t data)
415 {
416  uint8_t buffer[2];
417 
418  buffer[0] = data >> 8;
419  buffer[1] = data;
420 
421  bc_i2c_memory_transfer_t transfer;
422 
423  transfer.device_address = device_address;
424  transfer.memory_address = memory_address;
425  transfer.buffer = buffer;
426  transfer.length = 2;
427 
428  return bc_i2c_memory_write(channel, &transfer);
429 }
430 
431 bool bc_i2c_memory_read_8b(bc_i2c_channel_t channel, uint8_t device_address, uint32_t memory_address, uint8_t *data)
432 {
433  bc_i2c_memory_transfer_t transfer;
434 
435  transfer.device_address = device_address;
436  transfer.memory_address = memory_address;
437  transfer.buffer = data;
438  transfer.length = 1;
439 
440  return bc_i2c_memory_read(channel, &transfer);
441 }
442 
443 bool bc_i2c_memory_read_16b(bc_i2c_channel_t channel, uint8_t device_address, uint32_t memory_address, uint16_t *data)
444 {
445  uint8_t buffer[2];
446 
447  bc_i2c_memory_transfer_t transfer;
448 
449  transfer.device_address = device_address;
450  transfer.memory_address = memory_address;
451  transfer.buffer = buffer;
452  transfer.length = 2;
453 
454  if (!bc_i2c_memory_read(channel, &transfer))
455  {
456  return false;
457  }
458 
459  *data = buffer[0] << 8 | buffer[1];
460 
461  return true;
462 }
463 
464 static bool _bc_i2c_mem_write(I2C_TypeDef *i2c, uint8_t device_address, uint16_t memory_address, uint16_t memory_address_length, uint8_t *buffer, uint16_t length)
465 {
466  // Get maximum allowed timeout in ms
467  uint32_t timeout_ms = _BC_I2C_TX_TIMEOUT_ADJUST_FACTOR * bc_i2c_get_timeout_ms(i2c == I2C2 ? BC_I2C_I2C0 : BC_I2C_I2C1, length);
468 
469  _bc_i2c_timeout_begin(timeout_ms);
470 
471  // Wait until bus is not busy
472  if (!_bc_i2c_watch_flag(i2c, I2C_ISR_BUSY, SET))
473  {
474  return false;
475  }
476 
477  // Send slave address and memory address
478  if (!_bc_i2c_req_mem_write(i2c, device_address, memory_address, memory_address_length))
479  {
480  return false;
481  }
482 
483  // Set size of data to write
484  _bc_i2c_config(i2c, device_address, length, _BC_I2C_AUTOEND_MODE, _BC_I2C_NO_STARTSTOP);
485 
486  // Perform I2C transfer
487  return _bc_i2c_write(i2c, buffer, length);
488 }
489 
490 static bool _bc_i2c_mem_read(I2C_TypeDef *i2c, uint8_t device_address, uint16_t memory_address, uint16_t memory_address_length, uint8_t *buffer, uint16_t length)
491 {
492  // Get maximum allowed timeout in ms
493  uint32_t timeout_ms = _BC_I2C_RX_TIMEOUT_ADJUST_FACTOR * bc_i2c_get_timeout_ms(i2c == I2C2 ? BC_I2C_I2C0 : BC_I2C_I2C1, length);
494 
495  _bc_i2c_timeout_begin(timeout_ms);
496 
497  // Wait until bus is not busy
498  if (!_bc_i2c_watch_flag(i2c, I2C_ISR_BUSY, SET))
499  {
500  return false;
501  }
502 
503  // Send slave address and memory address
504  if (!_bc_i2c_req_mem_read(i2c, device_address, memory_address, memory_address_length))
505  {
506  return false;
507  }
508 
509  // Set size of data to read
510  _bc_i2c_config(i2c, device_address, length, I2C_CR2_AUTOEND, I2C_CR2_START | I2C_CR2_RD_WRN);
511 
512  // Perform I2C transfer
513  return _bc_i2c_read(i2c, buffer, length);
514 }
515 
516 static bool _bc_i2c_req_mem_write(I2C_TypeDef *i2c, uint8_t device_address, uint16_t memory_address, uint16_t memory_address_length)
517 {
518  _bc_i2c_config(i2c, device_address, memory_address_length, _BC_I2C_RELOAD_MODE, _BC_I2C_GENERATE_START_WRITE);
519 
520  // Wait until TXIS flag is set
521  if (!_bc_i2c_watch_flag(i2c, I2C_ISR_TXIS, RESET))
522  {
523  return false;
524  }
525 
526  // If memory address size is 16Bit
527  if (memory_address_length == _BC_I2C_MEMORY_ADDRESS_SIZE_16BIT)
528  {
529  // Send MSB of memory address
530  i2c->TXDR = (memory_address >> 8) & 0xff;
531 
532  // Wait until TXIS flag is set
533  if (!_bc_i2c_watch_flag(i2c, I2C_ISR_TXIS, RESET))
534  {
535  return false;
536  }
537  }
538 
539  // Send LSB of memory address
540  i2c->TXDR = memory_address & 0xff;
541 
542  // Wait until TCR flag is set
543  if (!_bc_i2c_watch_flag(i2c, I2C_ISR_TCR, RESET))
544  {
545  return false;
546  }
547 
548  return true;
549 }
550 
551 static bool _bc_i2c_req_mem_read(I2C_TypeDef *i2c, uint8_t device_address, uint16_t memory_address, uint16_t memory_address_length)
552 {
553  _bc_i2c_config(i2c, device_address, memory_address_length, _BC_I2C_SOFTEND_MODE, _BC_I2C_GENERATE_START_WRITE);
554 
555  // Wait until TXIS flag is set
556  if (!_bc_i2c_watch_flag(i2c, I2C_ISR_TXIS, RESET))
557  {
558  return false;
559  }
560 
561  // If memory address size is 16Bit
562  if (memory_address_length == _BC_I2C_MEMORY_ADDRESS_SIZE_16BIT)
563  {
564  // Send MSB of memory address
565  i2c->TXDR = (memory_address >> 8) & 0xff;
566 
567  // Wait until TXIS flag is set
568  if (!_bc_i2c_watch_flag(i2c, I2C_ISR_TXIS, RESET))
569  {
570  return false;
571  }
572  }
573 
574  // Send LSB of memory address
575  i2c->TXDR = memory_address & 0xff;
576 
577  // Wait until TC flag is set
578  if (!_bc_i2c_watch_flag(i2c, I2C_ISR_TC, RESET))
579  {
580  return false;
581  }
582 
583  return true;
584 }
585 
586 static void _bc_i2c_config(I2C_TypeDef *i2c, uint8_t device_address, uint8_t length, uint32_t mode, uint32_t Request)
587 {
588  uint32_t reg;
589 
590  // Get the CR2 register value
591  reg = i2c->CR2;
592 
593  // clear tmpreg specific bits
594  reg &= ~(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP);
595 
596  // update tmpreg
597  reg |= (device_address & I2C_CR2_SADD) | (length << I2C_CR2_NBYTES_Pos) | mode | Request;
598 
599  // update CR2 register
600  i2c->CR2 = reg;
601 }
602 
603 static bool _bc_i2c_watch_flag(I2C_TypeDef *i2c, uint32_t flag, FlagStatus status)
604 {
605  while ((i2c->ISR & flag) == status)
606  {
607  if ((flag == I2C_ISR_STOPF) || (flag == I2C_ISR_TXIS))
608  {
609  // Check if a NACK is not detected ...
610  if (!_bc_i2c_is_ack_failure(i2c))
611  {
612  return false;
613  }
614  }
615 
616  if (_bc_i2c_timeout_is_expired())
617  {
618  return false;
619  }
620  }
621  return true;
622 }
623 
624 static bool _bc_i2c_is_ack_failure(I2C_TypeDef *i2c)
625 {
626  if ((i2c->ISR & I2C_ISR_NACKF) != 0)
627  {
628  // Wait until STOP flag is reset
629  // AutoEnd should be initialized after AF
630  while ((i2c->ISR & I2C_ISR_STOPF) == 0)
631  {
632  if (_bc_i2c_timeout_is_expired())
633  {
634  return false;
635  }
636  }
637 
638  // Clear NACKF flag
639  i2c->ICR = I2C_ISR_NACKF;
640 
641  // Clear STOP flag
642  i2c->ICR = I2C_ISR_STOPF;
643 
644  // If a pending TXIS flag is set ...
645  if ((i2c->ISR & I2C_ISR_TXIS) != 0)
646  {
647  // ... write a dummy data in TXDR to clear it
648  i2c->TXDR = 0;
649  }
650 
651  // Flush TX register if not empty
652  if ((i2c->ISR & I2C_ISR_TXE) == 0)
653  {
654  i2c->ISR |= I2C_ISR_TXE;
655  }
656 
657  // Clear Configuration Register 2
658  i2c->CR2 &= ~(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN);
659 
660  return false;
661  }
662 
663  return true;
664 }
665 
666 static bool _bc_i2c_read(I2C_TypeDef *i2c, const void *buffer, size_t length)
667 {
668  uint8_t *p = (uint8_t *) buffer;
669 
670  while (length > 0)
671  {
672  // Wait until RXNE flag is set
673  if (!_bc_i2c_watch_flag(i2c, I2C_ISR_RXNE, RESET))
674  {
675  return false;
676  }
677 
678  // Read data from RXDR
679  *p++ = i2c->RXDR;
680 
681  length--;
682  }
683 
684  // No need to Check TC flag, with AUTOEND mode the stop is automatically generated
685 
686  // Wait until STOPF flag is reset
687  if (!_bc_i2c_watch_flag(i2c, I2C_ISR_STOPF, RESET))
688  {
689  return false;
690  }
691 
692  // Clear STOP flag
693  i2c->ICR = I2C_ICR_STOPCF;
694 
695  // Clear Configuration Register 2
696  i2c->CR2 &= ~(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN);
697 
698  return true;
699 }
700 
701 static uint32_t bc_i2c_get_timeout_ms(bc_i2c_channel_t channel, size_t length)
702 {
703  uint32_t timeout_us = bc_i2c_get_timeout_us(channel, length);
704 
705  return (timeout_us / 1000) + 10;
706 }
707 
708 static uint32_t bc_i2c_get_timeout_us(bc_i2c_channel_t channel, size_t length)
709 {
710  if (bc_i2c_get_speed(channel) == BC_I2C_SPEED_100_KHZ)
711  {
712  return _BC_I2C_BYTE_TRANSFER_TIME_US_100 * (length + 3);
713  }
714  else
715  {
716  return _BC_I2C_BYTE_TRANSFER_TIME_US_400 * (length + 3);
717  }
718 }
719 
720 static bool _bc_i2c_write(I2C_TypeDef *i2c, const void *buffer, size_t length)
721 {
722  uint8_t *p = (uint8_t *) buffer;
723 
724  while (length > 0)
725  {
726  // Wait until TXIS flag is set
727  if (!_bc_i2c_watch_flag(i2c, I2C_ISR_TXIS, RESET))
728  {
729  return false;
730  }
731 
732  // Write data to TXDR
733  i2c->TXDR = *p++;
734 
735  length--;
736  }
737 
738  // No need to Check TC flag, with AUTOEND mode the stop is automatically generated
739 
740  // Wait until STOPF flag is reset
741  if (!_bc_i2c_watch_flag(i2c, I2C_ISR_STOPF, RESET))
742  {
743  return false;
744  }
745 
746  // Clear STOP flag
747  i2c->ICR = I2C_ICR_STOPCF;
748 
749  // Clear Configuration Register 2
750  i2c->CR2 &= ~(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN);
751 
752  return true;
753 }
754 
755 void _bc_i2c_timeout_begin(uint32_t timeout_ms)
756 {
757  tick_timeout = bc_tick_get() + timeout_ms;
758 }
759 
760 bool _bc_i2c_timeout_is_expired(void)
761 {
762  bool is_expired = tick_timeout < bc_tick_get() ? true : false;
763 
764  return is_expired;
765 }
766 
767 static void _bc_i2c_restore_bus(I2C_TypeDef *i2c)
768 {
769  // TODO Take care of maximum rate on clk pin
770 
771  if (i2c == I2C2)
772  {
773  GPIOB->MODER &= ~GPIO_MODER_MODE10_Msk;
774  GPIOB->MODER |= GPIO_MODER_MODE10_0;
775  GPIOB->BSRR = GPIO_BSRR_BS_10;
776 
777  GPIOB->MODER &= ~GPIO_MODER_MODE11_Msk;
778 
779  while (!(GPIOB->IDR & GPIO_IDR_ID11))
780  {
781  GPIOB->ODR ^= GPIO_ODR_OD10;
782  }
783 
784  GPIOB->BSRR = GPIO_BSRR_BR_11;
785  GPIOB->BSRR = GPIO_BSRR_BS_11;
786 
787  // Configure I2C peripheral to transmit softend mode
788  _bc_i2c_config(i2c, 0xfe, 1, I2C_CR2_STOP, _BC_I2C_SOFTEND_MODE);
789 
790  // Reset I2C peripheral to generate STOP conditions immediately
791  __BC_I2C_RESET_PERIPHERAL(i2c);
792 
793  GPIOB->MODER &= ~GPIO_MODER_MODE10_Msk;
794  GPIOB->MODER |= GPIO_MODER_MODE10_1;
795 
796  GPIOB->MODER &= ~GPIO_MODER_MODE11_Msk;
797  GPIOB->MODER |= GPIO_MODER_MODE11_1;
798 
799  GPIOB->BSRR = GPIO_BSRR_BR_10;
800  GPIOB->BSRR = GPIO_BSRR_BR_11;
801  }
802  else
803  {
804  GPIOB->MODER &= ~GPIO_MODER_MODE8_Msk;
805  GPIOB->MODER |= GPIO_MODER_MODE8_0;
806  GPIOB->BSRR = GPIO_BSRR_BS_8;
807 
808  GPIOB->MODER &= ~GPIO_MODER_MODE9_Msk;
809 
810  while (!(GPIOB->IDR & GPIO_IDR_ID9))
811  {
812  GPIOB->ODR ^= GPIO_ODR_OD9;
813  }
814 
815  GPIOB->BSRR = GPIO_BSRR_BR_9;
816  GPIOB->BSRR = GPIO_BSRR_BS_9;
817 
818  // Configure I2C peripheral to transmit softend mode
819  _bc_i2c_config(i2c, 0xfe, 1, I2C_CR2_STOP, _BC_I2C_SOFTEND_MODE);
820 
821  // Reset I2C peripheral to generate STOP conditions immediately
822  __BC_I2C_RESET_PERIPHERAL(i2c);
823 
824  GPIOB->MODER &= ~GPIO_MODER_MODE8_Msk;
825  GPIOB->MODER |= GPIO_MODER_MODE8_1;
826 
827  GPIOB->MODER &= ~GPIO_MODER_MODE9_Msk;
828  GPIOB->MODER |= GPIO_MODER_MODE9_1;
829 
830  GPIOB->BSRR = GPIO_BSRR_BR_8;
831  GPIOB->BSRR = GPIO_BSRR_BR_11;
832  }
833 }
void * buffer
Pointer to buffer which is being written or read.
Definition: bc_i2c.h:66
I2C transfer parameters.
Definition: bc_i2c.h:42
uint64_t bc_tick_t
Timestamp data type.
Definition: bc_tick.h:16
bool bc_i2c_memory_write_16b(bc_i2c_channel_t channel, uint8_t device_address, uint32_t memory_address, uint16_t data)
Memory write 2 bytes to I2C channel.
Definition: bc_i2c.c:414
I2C communication speed is 400 kHz.
Definition: bc_i2c.h:36
GPIO channel P5.
Definition: bc_gpio.h:30
Channel has pull-up 4k7.
bool bc_module_sensor_set_pull(bc_module_sensor_channel_t channel, bc_module_sensor_pull_t pull)
Set pull of Sensor Module channel.
void bc_ds28e17_deinit(bc_ds28e17_t *self)
Deinitialize DS28E17.
Definition: bc_ds28e17.c:27
bool bc_ds28e17_set_speed(bc_ds28e17_t *self, bc_i2c_speed_t speed)
Set I2C speed.
Definition: bc_ds28e17.c:37
Channel has no pull.
I2C channel I2C0.
Definition: bc_i2c.h:18
bc_i2c_speed_t bc_i2c_get_speed(bc_i2c_channel_t channel)
Get speed I2C channel.
Definition: bc_i2c.c:189
uint8_t device_address
7-bit I2C device address
Definition: bc_i2c.h:45
bool bc_i2c_memory_read(bc_i2c_channel_t channel, const bc_i2c_memory_transfer_t *transfer)
Memory read from I2C channel.
Definition: bc_i2c.c:365
bool bc_i2c_read(bc_i2c_channel_t channel, const bc_i2c_transfer_t *transfer)
Read from I2C channel.
Definition: bc_i2c.c:283
bool bc_i2c_memory_read_8b(bc_i2c_channel_t channel, uint8_t device_address, uint32_t memory_address, uint8_t *data)
Memory read 1 byte from I2C channel.
Definition: bc_i2c.c:431
bool bc_ds28e17_read(bc_ds28e17_t *self, const bc_i2c_transfer_t *transfer)
Read from I2C.
Definition: bc_ds28e17.c:73
void bc_i2c_init(bc_i2c_channel_t channel, bc_i2c_speed_t speed)
Initialize I2C channel.
Definition: bc_i2c.c:54
void bc_i2c_deinit(bc_i2c_channel_t channel)
Deitialize I2C channel.
Definition: bc_i2c.c:139
bc_module_sensor_revision_t bc_module_sensor_get_revision(void)
Get Sensor Module revision.
bool bc_module_sensor_set_vdd(bool on)
Set VDD On / Off.
I2C communication speed is 100 kHz.
Definition: bc_i2c.h:33
void bc_ds28e17_init(bc_ds28e17_t *self, bc_gpio_channel_t channel, uint64_t device_number)
Initialize DS28E17.
Definition: bc_ds28e17.c:14
bc_tick_t bc_tick_get(void)
Get absolute timestamp since start of program.
Definition: bc_tick.c:7
void * buffer
Pointer to buffer which is being written or read.
Definition: bc_i2c.h:48
bool bc_i2c_write(bc_i2c_channel_t channel, const bc_i2c_transfer_t *transfer)
Write to I2C channel.
Definition: bc_i2c.c:237
uint32_t memory_address
8-bit I2C memory address (it can be extended to 16-bit format if OR-ed with BC_I2C_MEMORY_ADDRESS_16_...
Definition: bc_i2c.h:63
uint8_t device_address
7-bit I2C device address
Definition: bc_i2c.h:60
DS28E17 instance.
Definition: bc_ds28e17.h:14
I2C memory transfer parameters.
Definition: bc_i2c.h:57
bc_i2c_channel_t
I2C channels.
Definition: bc_i2c.h:15
void bc_i2c_set_speed(bc_i2c_channel_t channel, bc_i2c_speed_t speed)
Set I2C channel speed.
Definition: bc_i2c.c:194
size_t length
Length of buffer which is being written or read.
Definition: bc_i2c.h:51
Hardware revision R1.1.
bool bc_ds28e17_write(bc_ds28e17_t *self, const bc_i2c_transfer_t *transfer)
Write to I2C.
Definition: bc_ds28e17.c:62
Channel has pull-up 56R.
bc_i2c_speed_t
I2C communication speed.
Definition: bc_i2c.h:30
bool bc_ds28e17_memory_write(bc_ds28e17_t *self, const bc_i2c_memory_transfer_t *transfer)
Memory write to I2C.
Definition: bc_ds28e17.c:84
I2C channel I2C1.
Definition: bc_i2c.h:21
size_t length
Length of buffer which is being written or read.
Definition: bc_i2c.h:69
bool bc_i2c_memory_write(bc_i2c_channel_t channel, const bc_i2c_memory_transfer_t *transfer)
Memory write to I2C channel.
Definition: bc_i2c.c:327
bool bc_module_sensor_init(void)
Initialize Sensor Module.
I2C channel 1wire.
Definition: bc_i2c.h:24
bool bc_i2c_memory_read_16b(bc_i2c_channel_t channel, uint8_t device_address, uint32_t memory_address, uint16_t *data)
Memory read 2 bytes from I2C channel.
Definition: bc_i2c.c:443
#define BC_I2C_MEMORY_ADDRESS_16_BIT
This flag extends I2C memory transfer address from 8-bit to 16-bit.
Definition: bc_i2c.h:11
bool bc_ds28e17_memory_read(bc_ds28e17_t *self, const bc_i2c_memory_transfer_t *transfer)
Memory read from I2C.
Definition: bc_ds28e17.c:109
bool bc_i2c_memory_write_8b(bc_i2c_channel_t channel, uint8_t device_address, uint32_t memory_address, uint8_t data)
Memory write 1 byte to I2C channel.
Definition: bc_i2c.c:402